The present invention relates to a semiconductor memory and, more particularly, to a synchronous dynamic random access memory which is capable of accessing data in a memory cell array disposed therein in synchronism with a system clock from an external system such as a central processing unit (CPU).
A computer system generally includes a CPU for executing instructions on given tasks and a main memory for storing data, programs or the like requested by the CPU. To enhance the performance of the computer system, it is basically requested to increase the operating speed of the CPU and also make an access time to the main memory as short as possible, so that the CPU can operate at least with no wait states. Operation clock cycles of modern CPUs such as recent microprocessors are shortening more and more as clock frequencies of 33, 66, 100 MHZ or the like. However, the operating speed of a high density DRAM, which is still the cheapest memory on a price-per-bit base and using as a main memory device, has not been able to keep up with that of the CPU being speeded up. DRAM inherently has a minimum {overscore (RAS)} access time, i.e., the minimum period of time between activation of {overscore (RAS)}, upon which the signal {overscore (RAS)} changes from a high level to a low level, and the output of data from a chip thereof with column addresses latched by activation of {overscore (CAS)}. Such a {overscore (RAS)} access time is called a {overscore (RAS)} latency, and the time duration between the activation of the signal {overscore (CAS )} and the output of data therefrom called a {overscore (CAS)} latency. Moreover, a precharging time is required prior to re-access following the completion of a read operation or cycle. These factors decrease the total amount of operation speed of the DRAM, thereby causing the CPU to have wait states.
To compensate for the gap between the operation speed of the CPU and that of the main memory like the DRAM, the computer system includes an expensive high-speed buffer memory such as a cache memory which is arranged between the CPU and the main memory. The cache memory stores information data from the main memory which is requested by the CPU. Whenever the CPU issues the request for the data, a cache memory controller intercepts it and checks the cache memory to see if the data is stored in the cache memory. If the requested data exists therein, it is called a cache hit, and high-speed data transfer is immediately performed from the cache memory to the CPU. Whereas if there is no presence therein, it is called a cache miss, and the cache memory controller reads out the data from the slower main memory. The read-out data is stored in the cache memory and sent to the CPU. Thus, a subsequent request for this data may be immediately read out from the cache memory. That is, in case of the cache hit, the high-speed data transfer may be accomplished from the cache memory. However, in case of the cache miss, the high-speed data transfer from the main memory to the CPU cannot be expected, thereby incurring wait states of the CPU. Thus, it is extremely important to design DRAMs serving as the main memory to accomplish high-speed operations.
The data transfer between DRAMs and the CPU or the cache memory is accomplished with sequential information or data blocks. To transfer the continuous data at a high speed, various kinds of operating modes such as page, static column, nibble mode or the like have implemented in the DRAM. These operating modes are disclosed in U.S. Pat. Nos. 3,969,706 and 4,750,839. The memory cell array of the DRAM with the nibble mode is divided into four equal parts so that a plurality of memory cells can be made access with the same address. Data is temporarily stored in a shift register to be sequentially read out or written into. However, since the DRAM with the nibble mode cannot continuously transfer more than 5-bit data, the flexibility of the system design cannot be offered upon the application to high-speed data transfer systems. The page mode and the static column mode, after the selection of the same row address in a {overscore (RAS)} timing, can sequentially access column addresses in synchronism with {overscore (CAS)} toggling or cycles and with the transition detections of column addresses, respectively. However, since the DRAM with the page or the static column mode needs extra time, such as a setup and a hold times of the column address, for receiving the next new column address after the selection of a column address, it is impossible to access the continuous data at a memory bandwidth higher than 100 Mbits/sec., i.e., to reduce a {overscore (CAS )} cycle time below 10 nsec. Also, since the arbitrary reduction of the {overscore (CAS)} cycle time in the page mode cannot guarantee a sufficient column selection time to write data into selected memory cells during a write operation, error data may be written thereinto. However, since these high-speed operation modes are not operations synchronous to the system clock of the CPU, the data transfer system must use a newly designed DRAM controller whenever a CPU having higher speed is replaced. Thus, to keep up with high-speed microprocessors such as CISC and RISC types, the development of a synchronous DRAM is required which is capable of accessing the data synchronous to the system clock of the microprocessor at a high speed. An introduction to synchronous DRAMs appears with no disclosure of detailed circuits in the NIKKEI MICRODEVICES in April, 1992, Pages 158-161.
To increase the convenience of use and also enlarge the range of applications, it is more desirable to allow an on-chip synchronous DRAM to not only operate at various frequencies of the system clock, but also be programmed to have various operation modes such as a latency depending on each clock frequency, a burst length or size defining the number of output bits, a column addressing way or type, and so on. Examples for selecting an operation mode in DRAM are disclosed in U.S. Pat. No. 4,833,650 issued on May 23, 1989, as well as in U.S. Pat. No. 4,987,325 issued on Jan. 22, 1991 and assigned to the same assignee. These prior art patents disclose technologies to select one operation mode, such as page, static column and nibble modes. Selection of the operation mode in these prior art patents is performed by cutting off fuse elements by means of a laser beam from an external laser apparatus or an electric current from an external power supply, or by selectively wiring bonding pads. However, in these prior technologies, once the operation mode had been selected, the selected operation mode cannot be changed into another operation mode. Thus, the prior art does not permit changes between operation modes even if subsequently required.
An object of the present invention is to provide a synchronous dynamic random access memory in which input/output of data is synchronous with an external system clock.
Another object of the present invention is to provide a synchronous dynamic random access memory with high performance.
Still another object of the present invention is to provide a synchronous dynamic random access memory which is capable of operating at a high data transfer rate.
A further object of the present invention is to provide a synchronous dynamic random access memory which is able of operating at various system clock frequencies.
Still a further object of the present invention is to provide a synchronous dynamic random access memory in which the number of input or output data may be programmed.
Another object of the present invention is to provide a counter circuit in which a counting operation can be performed in either binary or interleave mode.
Still another object of the present invention is to provide a semiconductor memory which can prohibit unnecessary internal operations of the memory chip regardless of the number of input or output data.
A further object of the present invention is to provide a semiconductor memory which can set various operation modes.
Still a further object of the present invention is to provide a semiconductor memory including a data transfer circuit for providing precharge and data transfer operable at a high data transfer rate.
Another object of the present invention is to provide a semiconductor memory which includes at least two memory banks whose operation modes can be set in on-chip semiconductor memory.
According to an aspect of the present invention, a semiconductor memory formed on a semiconductor chip having various operation modes, includes address input circuit for receiving external address designating at least one of the operation modes to the chip, a circuit for generating a mode set control signal in a mode set operation; and a circuit for storing codes based on the external address in response to the mode set control signal and producing an operation mode signal representing the operation mode determined by the codes.
According to another aspect of the present invention, a semiconductor memory having a plurality of internal operation modes includes a circuit for producing a power-on signal upon reaching of a power supply potential at a predetermined value after the application of the power supply potential, and a circuit for automatically storing a plurality of code signals in response to the power-on signal and producing internal operation mode signals indicating selected ones of the internal operation modes which are defined by the code signals.
According to another aspect of the present invention, a dynamic random access memory includes a plurality of memory banks, each bank including a plurality of memory cells and operable in either an active cycle indicating a read cycle or a write cycle, or a precharge cycle, a first circuit for receiving a row address strobe signal and producing a first signal, a second circuit for receiving a row address strobe signal and producing a first signal, a second circuit for receiving a column address strobe signal and producing a second signal, a third circuit for receiving a write enable signal and producing a third signal, an address input circuit for receiving address indicating the selection of the memory banks, and a logic circuit responsive to the first, second and third signals and the address signals including a latch circuit corresponding to the respective banks for storing data representing the active cycle for the bank selected by the address and data representing the precharge cycle for unselected banks.
According to still another aspect of the present invention, a dynamic random access memory receiving an external clock includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle indicating a read cycle or a write cycle, or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to one of a rising edge and a falling edge of the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level from the receiving and latching circuit and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
According to still another aspect of the present invention, a semiconductor memory formed on a semiconductor chip receiving an external clock to the chip and outputting data read out from memory cells via data output buffer circuit, includes a circuit for generating a burst length signal representing the time interval of output of data and outputting data in synchronism with the clock via the data output buffer circuit during the time interval corresponding to the burst length signal.
According to further still another aspect of the present invention, a semiconductor memory includes a memory array having a plurality of memory cells arranged in rows and columns, a plurality of sub-arrays provided by partitioning the memory cell array in the row direction, each of the sub-arrays having a plurality of word lines respectively connected to associated columns of the memory cells and a plurality of bit lines respectively connected to associated rows of the memory cells, the bit lines of each sub-array divided into first groups of bit lines and second groups of bit lines, the respective ones of which are divided into first sub-groups of bit lines and second sub-groups of bit lines, the first groups of each sub-array alternately arranged with the second groups thereof, the first sub-groups of each sub-array alternately arranged with the second sub-groups thereof, and I/O buses respectively disposed in parallel to the word lines between the sub-arrays and on outer sides of the sub-arrays, and divided into first I/O buses and second I/O buses respectively arranged at odd and even positions, each I/O bus divided into first I/O lines and second I/O lines, the first and the second I/O lines of the respective first I/O buses respectively connected via column selection switches with the bit lines of the first and the second sub-groups of the first groups of sub-arrays adjacent thereto, the first and the second I/O lines of the respective second I/O buses respectively connected via column selection switches with the bit lines of the first and the second sub-groups of the second groups of sub-arrays adjacent thereto.